? ? datel, inc., mansfield, ma 02048 ( usa ) tel: (508) 339-3000, (800)233-2765 fax: (508) 339-6356 email: sales@datel.com internet: www.datel.com adc-318, ADC-318A 8-bit, 120mhz and 140mhz full-flash a/d converter fea tures low power dissipation (960mw max.) ttl compatible output diff./integral nonlinearity (?lsb max.) 1:2 demultiplexed straight output programmable 2:1 frequency divided ttl clock output with reset surface mount package selectable input logic (ttl, ecl, pecl) +5v or 5v power supply operation figure 1. adc-318/318a functional block diagram 1 ?dvs (digital) 48 rset ecl/pecl 2 ref. bottom (v rb ) 47 rset ecl/pecl 3 analog ground 46 rset ttl 4 ref. mid point (v rm1 ) 45 select 5 +av s (analog) 44 inv 6 analog in (v in ) 43 ttl clock out 7 ref. mid point (v rm2 ) 42 +dv s 2 (digital) 8 +av s (analog) 41 digital ground 2 9 ref. mid point (v rm3 ) 40 a bit 1 (msb) 10 analog ground 39 a bit 2 11 ref. top (v rt ) 38 a bit 3 12 digital ground 3 37 a bit 4 13 a/d clock ecl/pecl 36 a bit 5 14 a/d clock ecl/pecl 35 a bit 6 15 a/d clock ttl 34 a bit 7 16 no connection 33 a bit 8 (lsb) 17 no connection 32 digital ground 2 18 no connection 31 +dv s 2 (digital) 19 +dv s 2 (digital) 30 +dv s 1 (digital) 20 digital ground 2 29 digital ground 1 21 b bit 8 (lsb) 28 b bit 1 (msb) 22 b bit 7 27 b bit 2 23 b bit 6 26 b bit 3 24 b bit 5 25 b bit 4 input/output connections pin function pin function 256 e n c o d e r c o m p a r a t o r select 6 11 9 7 4 2 13 14 15 48 47 46 v in v rt v rm3 v rm2 v rm1 v rb a/d clock ecl/pecl a/d clock ttl rset ecl/pecl rset ttl r e s i s t o r m a t r i x 6 - b i t l a t c h a n d e n c o d e r 6 6 6 6 delay d q q 8 8 6 a latch b latch a ttl output b ttl output ttl 44 inv 33 bit 8 (lsb) 34 bit 7 35 bit 6 36 bit 5 a output 37 bit 4 38 bit 3 39 bit 2 40 bit 1 (msb) 21 bit 8 (lsb) 22 bit 7 23 bit 6 24 bit 5 b output 25 bit 4 26 bit 3 27 bit 2 28 bit 1 (msb) 43 clock out 45 select a/d clock ecl/pecl rset ecl/pecl general description the adc-318 and ADC-318A are 8 bit monolithic bipolar, full flash a/d converters. though they have high, 120mhz (adc-318) and 140mhz (ADC-318A), sampling rates, their input logic level, including the start convert pulse, is ttl, ecl and pecl compatible. digital outputs are also ttl compatible and allow a straight output or a programmable 1:2 de-multiplexed output. the adc-318 and ADC-318A feature 1/2 lsb max. integral and differential non-linearity, +5v single or 5v dual power supply operation, a low 960mw maximum power dissipation, 150mhz wide analog input range and excellent temperature coefficient in a small 48 pin qfp package. the start convert pulse can have a 50% duty cycle. the adc-318 and ADC-318A offer low cost, easy to use functionality for design engineers.
adc-318, ADC-318A 2 ? ? digital inputs min. typ. max. units a/d clock pulse width (t pw1 ) adc-318 3.2 ? ? ns ADC-318A 3.0 ? ? ns a/d clock pulse width (t pw0 ) adc-318 3.2 ? ? ns ADC-318A 3.0 ? ? ns rset setup time (t rs ) 3.5 ? ? ns rset hold time (t rh ) 0 ? ? ns digital outputs output voltage "1" (@?2ma) 2.4 ? ? volts output voltage "0" (@1ma) ? ? +0.5 volts output rise time (t r ) ? ? 2 ? ns output fall time (t f ) ? ? 2 ? ns output delay (t do1 ) ? 1/fc 1/f c +1 1/f c +2 ns output delay (t do2 ) ? 6.5 8 10 ns clockout output delay (t dclk ) ? 4.5 7 8 ns performance resolution 8 ? ? bit conversion rate (f s ) straight mode adc-318 100 ? ? mhz ADC-318A 100 ? ? mhz de-multiplexed mode adc-318 100 ? ? mhz ADC-318A 100 ? ? mhz sampling delay (t ds ) 3 4.5 6 ns aperture jitter (taj) ? 10 ? ps integral linearity error ? ? 0.5 lsb diff. linearity error ? ? 0.5 lsb s/n ratio ? adc-318 (@f in = 1khz) ? 46 ? db (@f in = 29.999mhz) ? 40 ? db ADC-318A (@f in = 1khz) ? 46 ? db (@f in = 34.999mhz) ? 40 ? db error rate adc-318 (@f in = 1khz) ? ? 10 -12 tps (@f in = 29.999mhz) ? ? 10 -9 tps (@fin = 24.999mhz) ? ? 10 -9 tps ADC-318A (@f in = 1khz) ? ? 10 -12 tps (@f in = 34.999mhz) ? ? 10 -9 tps (@fin = 24.999mhz) ? ? 10 -9 tps power requirements supply voltage one power supply (+av s , +dv s 1,2) +4.75 +5.0 +5.25 volts one power supply (dgnd3) +4.75 +5.0 +5.25 volts one power supply (?dv s ) ? 0.05 0 +0.05 volts two power supply (+av s , +dv s 1,2) +4.75 +5.0 +5.25 volts two power supply (dgnd3) ?0.05 0 +0.05 volts two power supply (?dv s ) ?5.5 ?5.0 ? 4.75 volts adc-318 supply current (+i s ) 125 145 185 ma supply current (?i s ) 0.4 0.6 0.8 ma ADC-318A supply current (+z s ) 110 150 185 ma supply current (?z s ) 0.4 0.6 0.8 ma analog inputs min. typ. max. units input voltage ? +2 to +4 ? volts input resistance 4 ? 50 k w input current 0 ? 500 a input capacitance ? 21 ? pf input bandwidth v in = 2v p-p, ?3db 150 ? ? mhz reference inputs reference voltage vrt +2.9 ? +4.1 volts vrb +1.4 ? +2.6 volts vrt?vrb 1.5 ? 2.1 volts reference resistance 75 115 155 w reference current 9.7 17.4 28 ma v rt offset voltage 2 ? 15 mv v rb offset voltage 2 ? 10 mv digital inputs ecl, pecl input voltage "1" dgnd3?1.05 ? dgnd3?0.5 volts input voltage "0" dgnd3?3.2 ? dgnd3?1.4 volts threshold voltage ? dgnd3?1.2 ? volts input current "1" ?50 ? +50 a input current "0" ?75 ? 0 a voltage difference 0.4 0.8 ? volts ttl input voltage "1" +2.0 ? ? volts input voltage "0" ? ? +0.8 volts threshold voltage ? +1.5 ? volts input current "1" a ?50 ? 0 a input current "0" a ?500 ? 0 a select input voltage "1" ? +dvs1 ? output voltage "0" ? +dgnd1 ? input capacitance ? ? 5 pf p arameters limits units supply voltage (+avs, +dvs, 1,2) ?0.5 to +7.0 volts supply voltage (agnd, dgnd 1, 2) ?0.5 to +7.0 volts supply voltage (dgnd 3) ?0.5 to +7.0 volts supply voltage (?dvs) ?0.5 to +7.0 volts supply voltage (?dvs) ?7.0 to +0.5 volts reference voltage (vrt) +2.7 to +avs volts reference voltage (vrb) vin ?2.7 to +avs reference voltage (vrt?vrb1) 2.5 volts input voltage, analog (vin) vrt ?2.7 to +avs volts input voltage, digital ecl ?dvs to +0.5 volts pecl ?0.5 to dgnd3 volts ttl ?0.5 to +dvs1 volts diff. voltage between pin a 2.7 volts power dissipation, max. ? 2 w absolute maximum ra tings footnote: single supply dual supply a a/d clock?a/d clock and reset?reset of ecl/pecl logic inputs. ? with adc-318 mounted on a 50x50mm glass fiber base epoxy board, 1.6mm thick. functional specifica tions (typical at t a = 25c, v rt = +4v, v rb = +2v, dgnd3 = +dv s1= +dvs2 = +av s = +5v, ?dv s = 0v, pecl logic, unless otherwise specified.) 13 13 13 1 1 1 1 1 1 1 1 1 1 1 1
adc-318, ADC-318A 3 ? ? 318a requires that the characteristic impedance of all input/ output logic and analog input lines be properly matched. 2. power supply lines and grounding may effect the perfor- mance of the adc-318 and ADC-318A. separate and substantial agnd and dgnd ground planes are required. these grounds have to be connected to one earth point underneath the device. there are three digital grounds, dgnd1 (pin 29), dgnd2 (pins 20, 32, 41) and dgnd3 (pin 12). these dgnd 's are separated internally. dgnd1 and dgnd2 are always connected externally but dgnd3 shall be connected differently depending on whether the single or dual power supply mode is used, as explained later. the adc-318 and ADC-318A have separate +avs and +dvs pins. it is recommended that both +avs and +dvs be powered from a single source. other external digital circuits must be powered with a separate +dvs. layouts of +avs and +dvs lines must be separated like the gnd lines to avoid mutual interference and are connected to a point through an lc filter. there are two digital supplies +dvs1 (pin 30) and +dvs2 (pins 19, 31, 42). these are also separated internally. these must be tied together outside while in use. b ypassing all power lines with a 0.1uf ceramic chip capacitor and the use of multilayered pc boards is recommended. 3. the analog input terminal (pin 6) has 21pf of input capaci- tance. the input signal has to be given via a buffer amplifier which has enough driving power. make lead wires as short as possible and use chip resistors and capacitors to avoid parasitic capacitance and inductance. 4. the use of a buffer amplifier and bypass capacitors is also recommended on the reference input terminals vrt (pin 11) and vrb (pin 2). the analog input range is determined by power requirements (cont.) power dissipation adc-318 680 780 980 mw ADC-318A 570 790 960 mw parameters operating temp. range, case adc-318, 318a ?20 ? +75 c thermal impedance q ja ? 62.5 ? c/watt storage temperature range ? 65 ? +150 c package type 48-pin, plastic qfp weight 0.25 ounces (0.7 grams) footnotes: vin = +3v +0.07vrms vih = dgnd3?0.8v vil = dgnd3?1.6v a vih = 3.5v vil = 0.2v ? ttl, 0.8 to 2.0v, cl = 5pf ? dmux mode, cl = 5pf; fc = clock frequency ? straight mode, cl = 5pf ? cl = 5pf ? vin = fs, dmux mode vin = fs, dmux mode, error >16lsb vin = fs, straight mode, error >16lsb "times per sample" mounted on 50x50mm, 1.6mm thick glass fiber base epoxy board technical no tes 1. the adc-318 and ADC-318A are ultra high speed full flash a/d converters that have 120mhz and 140mhz sampling rates respectively. the adc-318 and ADC-318A are fully interchangeable products with the exception of their sampling rates. their inputs are ttl, ecl and pecl compatible and their outputs are ttl compatible. obtaining fully specified performance from the adc-318 and adc- 1 2 1 1 1 2 figure 2-1: one power supply operation (ttl, pecl) figure 2-2: two power supply operation (ecl) note: all capacitors not otherwise designated are 0.1f + + + + 5v(a) 10 f 10 h 5v(d) 10 f 8 5 19 30 31 42 10 f 2 v rb +2v analog in +2v to +4v 4 6 7 9 11 vrt +4v 10 f a/d clock 15 13 14 48 47 46 3 10 20 29 32 41 45 44 43 ttl clock out 5v(d) 28 b bit 1 27 b bit 2 26 b bit 3 25 b bit 4 24 b bit 5 23 b bit 6 22 b bit 7 21 b bit 8 lsb msb 40 a bit 1 39 a bit 2 38 a bit 3 37 a bit 4 36 a bit 5 35 a bit 6 34 a bit 7 33 a bit 8 lsb msb adc-318 12 1 ttl pecl ADC-318A 5v(d) + + + + + 5v(a) 10 f 10 h 5v(d) 10 f 8 5 19 30 31 42 10 f 2 v rb +2v analog in +2v to +4v 4 6 7 9 11 vrt +4v 10 f ecl a/d clock a/d clock 15 13 14 48 47 46 3 10 1 12 20 29 32 41 10 f 5v(d) 45 44 43 ttl clock out 28 b bit 1 27 b bit 2 26 b bit 3 25 b bit 4 24 b bit 5 23 b bit 6 22 b bit 7 21 b bit 8 lsb msb 40 a bit 1 39 a bit 2 38 a bit 3 37 a bit 4 36 a bit 5 35 a bit 6 34 a bit 7 33 a bit 8 lsb msb adc-318 ADC-318A 5v(d) 5v(d)
adc-318, ADC-318A 4 ? ? figure 2-3: a/d clock input connection figure 2-4: digital input/output connections signal digital output code (a,b output) input inv=1 inv=0 voltage lsb msb lsb msb vrt 11111111 00000000 vrm2 10000000 01111111 01111111 10000000 vrb 00000000 11111111 table 4: digital output coding digital input supply level ?dvs dgnd3 voltages ttl 0v +5v +5v pecl 0v +5v +5v ecl ?5v 0v 5v table 3: logic input level vs. power supply settings 11 12 13 14 15 16 17 18 ttl level clock input a/d clock a/d clock a/d clock ecl, pecl level clock inputs adc-318 ADC-318A ttl level reset input rset rset rset ecl, pecl level reset inputs 2 1 48 47 46 45 44 43 42 ttl clock out complementary binary straight binary output coding straight data out demultiplexed data out a/d conversion mode 5v(d) 5v(d) adc-318 ADC-318A the reference input voltages given to vrt and vrb. keep the ranges of v within values shown in this data sheet. standard settings are vrt = +4.0v, v input range from +2 to +4v. this setting can be varied to vrt = +3.5v, vrb = +2v and 1.5v p-p analog input range, depending on your selection of amplifiers which may provide less than +4v output. 5. the adc-318 and ADC-318A have resistor matrix taps at vrm1 (pin 4), vrm2 (pin 7) and vrm3 (pin 9). these pins provide ?, ? and ? full scale of vrt-vrb voltage respec- tively. these outputs may be used to adjust the integral non-linearity. bypass these pins to gnd with 0.1uf ceramic chip capacitors. 6. a/d clk input and rset/rset inputs are ttl or ecl, pecl (positive ecl) compatible. pins are provided individually. ttl or pecl is available with +5v single power applied. ecl is available with 5v dual power applied. the connections of ?dvs (pin 1) and dgnd3 (pin12) are different depending on the power supply mode used. refer to figures 2-1 and 2-2. a . for +5v single power (ttl or pecl) ?dvs (pin 1) is connected to dgnd. dgnd3 (pin 12) is connected to +5v power. b . for 5v dual power (ecl) ?dvs (pin 1) is connected to ?5v power. dgnd3 (pin 12) is connected to dgnd. 7. when the a/d clk is driven with ecl or pecl, a/d clk (pin 13) and a/d clk (pin 14) are to be driven by differen- tial logic inputs to avoid unstable performance at critically high speeds. if a risk of unstable performance is accept- able, single logic input can be used opening a/d clk (pin 14). the a/d clk pin should be bypassed to dgnd with a 0.1uf ceramic capacitor. when connected this way there will be a voltage of dgnd ?1.2v on the a/d clk pin. this voltage can not be used as a threshold voltage for ecl or pecl. input the a/d clk pulse to pin 15 when ttl is selected. 8. the adc-318 and ADC-318A have rset/rset input pins. an internal frequency half divider can be initialized with inputs to these pins. with ecl or pecl, differential inputs are given to rset (pin 48) and rset (pin 47). this function can be achieved with a single input, leaving pin 47 open and bypassing to dgnd with a 0.1uf ceramic chip capacitor. the voltage level of pin 47 is the threshold voltage of ecl or pecl. use rset (pin 46) for ttl. 9. select (pin 45) is used to set output mode. connection of this pin to dgnd selects the straight output mode and connection to +dvs selects the 1:2 de-multiplexed output mode. the maximum sampling rates are 100mhz for straight mode (for both models, adc-318 and ADC-318A) and 120mhz (adc-318) and 140mhz (ADC-318A) for de- multiplexed mode. refer to figure 2-4. there is an applica- tion where a multiple number of adc-318/318a's are used with a common a/d clk and outputs are in de-multiplexed mode. in this case, the initial conditions of the frequency half divider of each a/d converter are not synchronized and it is possible that each converter may have one clock maximum of timing lag. this lag can be avoided by giving a common rset pulse to all converters at power on. (see figure 3-3 and 3-4, timing diagrams.) 10.the adc-318 and ADC-318A have a ttl compatible clk out (pin 43). since the rising edge of this pulse can provide setup and hold time of output data, regardless of the output mode, this signal can be used as synchronization pulse for external circuits. data output timing is different for the straight mode and the de-multiplexed mode. see the timing chart figure 3. 11. inv (pin 44) is used to invert polarity of the ttl compatible output data from both a and b ports. leaving this pin open or connected to +dvs makes the output positive true and connection to dgnd makes it negative true logic. see input/output code table, table 4.
adc-318, ADC-318A 5 ? ? figure 3-1: demultiplexed data output (select-pin: +dvs or left open, 120mhz max. clock frequency) figure 3-2: straight data output (select-pin: dgnd, 100mhz max. clock frequency) figure 3-3: parallel operation without rset pulse figure 3-4: parallel operation using rset synchronization a/d clock clock out 1 data out 2 (a,b) clock out 2 data out 1 (a,b) a/d clock a/d clock adc-318/318a rset a/d clock clock out 1 data 1 (a, b) data 2 (a, b) clock out 2 a/d clock adc-318/318a rset (2) (1) 8 8 8 8 a/d clock clock out 1 data out 2 (a,b) clock out 2 data out 1 (a,b) rset a/d clock a/d clock adc-318/318a rset a/d clock a/d clock adc-318/318a rset rset 8 8 8 8 (2) (1) clock out 1 data 1 (a, b) data 2 (a, b) clock out 2 t ds n-1 n n+1 n+2 n+3 n+4 n+5 analog signal a in t pw1 t pw0 a data output b data output 3.5ns min. clock out rset a/d clock 3ns min. 6ns max t n+6 n+7 2.0v 0.8v 2.0v 0.8v reset period td clock 4.5ns min. 8ns max. 2.0v 0.8v tdo1 t t 0ns min. trh trs trh trs tdo2 n+3 n n+2 2.0v 0.8v t+2ns max. ~ ~ n+1 6.5ns min. 10ns max. tpw1, min tpw0, min 3.2ns 3.0ns 3.2ns 3.0ns 318 318a t ds n-1 n n+2 n+3 analog signal a in t pw 1 t pw 0 a data output clock out (inverted a/d clock out) rset a/d clock n+1 n-3 n-4 n-2 n-4 n-3 n-1 n-2 n n-1 t d clock 6.5ns min. 10ns max. b data output t 2.0v 0.8v n-5 2.0v 0.8v t do2 2.0v 0.8v 4.5ns min. 8ns max. 3ns min. 6ns max. tpw1, min tpw0, min 3.2ns 3.0ns 3.2ns 3.0ns 318 318a
adc-318, ADC-318A 6 ? ? application this device can be used in applications where 3 parallel channels are synchronized. conversion speed is the highest in the de-multiplexed mode. it is difficult to control timing of three channels at such a high speed. two practical ways to maintain timing for reading data into the system are given. 1. clock output of one a/d is used in reading data of other channels time delay of clock output and output data are specified as: td clk (clk out delay) ; 4.5nsec min., 8.0nsec max. tdo2 (output data delay); 6.5nsec min., 10nsec max. these values apply over the operating temperature and supply voltage ranges. timing control of tset (setup time) seems to be very critical. it tends to lead by 0.5nsec as temperature and supply voltages go lower. when a/d converters for 3 channels are used on the same board, temperature and supply voltages tend to change in the same direction and effects caused by these changes are negligible. a/d clck rset clk out output data (a, b) td clck min. 5.0ns (4.5ns) 7.5ns (8.0ns) 7.0ns (6.5ns) 9.5ns (10ns) th reset 14ns tset min. 2.5ns thold min. 6.5ns td clck max. tdo2 min. tdo2 max. tdclk and tdo2 at ta=25c , +vs=+5.0v are; td clk: 5.0nsec min., 7.5nsec max. tdo2: 7.0nsec min., 9.5nsec max. so long as devices are located on the same board and take power from the same source, 2.5nsec min. of setup time for data reading can be secured even though temperature and power supply voltages vary. a timing diagram at 140mhz sampling rate is shown in figure 4a. 2. to read output data of 3 channels into a gate array both output data lines and each clock output are read into a gate array if the digital circuits after the a/d conversion consist of one high speed gate array. an and gate is prepared to take the and of each output signal which is used for reading output data. the slowest rise time clock determines the system clock. thus adequate setup time is secured. this method can be employed only when a high speed gate array is used. the setup time is delayed by the delay time of the and gate. the use of a discrete ic gate is not recommended because of its time delay characteristics. see figure 4b figure 4a: timing diagram 1 figure 4b: timing diagram 2 *values in parenthesis are for the entire operating temperature and operating power supply ranges *values in parenthesis are for the entire operating temperature and operating power supply ranges a/d clck rset clk out output data (a, b) td clck min. 5.0ns (4.5ns) 7.5ns (8.0ns) 7.0ns (6.5ns) 9.5ns (10ns) th reset 14ns td clck max. tdo2 min. tdo2 max. tset min. 5.0ns+xns thold min. 6.5ns?xns gate array clk (clk out 1, clk out 2, clk out 3)
adc-318, ADC-318A 7 ? ? 1 . t h e e v a l u a t i o n c i r c u i t s h o w n e m p l o y s p e c l l o g i c . b e c a u s e o f t h i s , a 1 v p - p , 0 v c e n t e r , s i n e w a v e m u s t b e u s e d a s t h e c l o c k i n p u t ( a / d c l k ) a t c n 3 . 2 . w h e n a n a l o g s i g n a l s a r e t a k e n f r o m t h e c n 1 a m p l i f i e r i n p u t ? a ? m u s t b e l e f t o p e n w h i l e ? b ? i s s h o r t c i r c u i t e d . t h e a n a l o g i n p u t s i g n a l s a t c n 1 m u s t b e l e s s t h a n 8 0 0 m v p - p , 0 v a n d z e r o c e n t e r e d . t h e + a m p a n d ? a m p s u p p l y p i n s o n t h e i n p u t a m p l i f i e r a r e n o r m a l l y c o n n e c t e d t o + / - 5 v w h i c h , a l o n g w i t h t h e g a i n o f - 2 u s e d w i t h t h e c l c - 4 0 4 i n t h i s c i r c u i t , w i l l l i m i t t h e a m p l i f i e r s o u t p u t d y n a m i c r a n g e . t o i n c r e a s e t h e a m p l i f i e r s o u t p u t d y n a m i c r a n g e t h e + a m p p i n c a n b e c o n n e c t e d t o + 7 v a n d t h e ? a m p c o n n e c t e d t o - 3 v . v r t a n d v r b m a y r e q u i r e a d j u s t m e n t i n t h i s c a s e . 3 . w h e n a n a l o g s i g n a l s a r e i n p u t f r o m c n 2 , t h e d i r e c t i n p u t , a c c o u p l i n g c a n b e a c h i e v e d b y i n s e r t i n g a 0 . 1 f c a p a c i t o r a t ? a ? a n d a 1 0 k o h m r e s i s t o r a t ? b ? . i t i s n o t n e c e s s a r y t o b e c o n c e r n e d a b o u t t h e o u t p u t v o l t a g e o f t h e i n p u t a m p l i f i e r . v r t m a y b e l i m i t e d i n t h i s c a s e b y n j m 3 4 0 3 . t h e i n p u t v o l t a g e t o t h e n j m 3 4 0 3 a m p l i f i e r c a n b e a d j u s t e d t o c o r r e c t . b o t h v r t a n d v r b c a n b e t r i m m e d . figure 5: evaluation circuit diagram
datel, inc. 11 cabot boulevard, mansfield, ma 02048-1151 tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 internet: www.datel.com email: sales@datel.com data sheet fax back: (508) 261-2857 datel makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. specifications are subject to change without notice. the datel logo is a registered datel, inc. trademark. datel (uk) ltd. tadley, england tel: (01256)-880444 datel s.a.r.l. montigny le bretonneux, france tel: 01-34-60-01-01 datel gmbh munchen, germany tel: 89-544334-0 datel kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-354-2025 ds-0358 5/98 adc-318, ADC-318A ? ? iso 9001 iso 9001 registered .602 .016 (15.3) +.016 ?.004 .472 0.031 (0.8) 0.012 +.006 ?.004 48 37 36 25 24 13 12 1 0.004 +.008 ?.004 .531 (13.5) 0.006 +.004 ?.002 0.035 .008 0.087 +.014 ?.006 (12.0) (0.3) (2.2) (0.9) (0.1) (0.15) ordering information adc-318 8-bit, 120mhz flash a/d ADC-318A 8-bit, 140mhz flash a/d figure 6: typical performance curve mechanical dimensions inces (mm) 170 160 150 140 130 ?25 25 75 t a ?ambient temperature (c) 170 160 150 140 130 0 50 140 conversion rate (mhz) 100 20 15 10 ?25 25 75 10- 6 10- 7 10- 8 10- 9 10- 10 140 180 160 40 30 20 3 10 50 input frequency (mhz) 50 1 5 30 fig. 4-1: supply current vs. temperature s u p p l y c u r r e n t ( m a ) fig. 4-2: supply current vs. conversion rate s u p p l y c u r r e n t ( m a ) r e f e r e n c e c u r r e n t ( m a ) fig. 4-3: reference current vs. temperature fig. 4-4: error rate vs. conversion rate fig. 4-5: snr+thd vs. input signal frequency s n r + t h d ( d b ) t a ?ambient temperature (c) conversion rate (mhz) e r r o r r a t e ( t p s ) sine wave curvefit test 1.0000 (256) 0.0000 (128) 0.5000 (192) ?0.500 (64) v o l t / ( c o d e ) 8 7 6 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 d e v i a t i o n ( l s b ) s/n ratio 48.7db 7.8 effective bits conditions sampling frequency 120mhz signal frequency 996khz 4096 points ADC-318A adc-318 adc-318 ADC-318A fin = fc/4?1khz error> 16lsb 170 160 150 140 130 ?25 25 75 t a ?ambient temperature (c) fig. 4-8: maximum conversion rate vs. temperature c o n v e r s i o n r a t e ( m h z ) adc-318 ADC-318A adc-318: fc=120mhz ADC-318A: fc=140mhz 90 80 70 2 c 0 s n r + t h d ( d b ) fig. 4-6: allowable ambient temperature vs. air flow 1 3 m/s 60 four-layer board double-layer board single-layer board ADC-318A adc-318 200 100 0 2 3 4 v in pin voltage (v) fig. 4-7: analog input current vs. voltage inputs a n a l o g i n p u t c u r r e n t ( a ) vrt = +4v vrb = +2v fig. 4-9: sine wave curvefit test
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